The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices, and more particularly, preferred embodiments relate to semiconductor devices with a bonding pad section (an electrode for external connection) that has a characteristic structure and methods for manufacturing the same.
As semiconductor devices have been further miniaturized in recent years, wiring layers are formed in multiple layers in many more occasions. In a process for manufacturing semiconductor devices, the number of process steps for forming wiring layers and contact layers for electrically connecting the wiring layers has increased with respect to the total number of process steps required for manufacturing the semiconductor devices. Accordingly, the method for forming wiring layers and contact layers has currently become an important issue in the process for manufacturing semiconductor devices. So-called damascene methods are known among methods that facilitate the formation of wiring layers and contact layers.
In a damascene method, specified wiring grooves are formed in a dielectric layer, a wiring material such as aluminum alloy or copper is deposited in the wiring grooves, excess portions of the wiring material are polished and removed by a chemical-mechanical polishing method (hereafter referred to as a xe2x80x9cCMPxe2x80x9d method) to embed the wiring material in the wiring grooves to form wiring layers. In particular, when copper is used as the wiring material, a reactive ion etching is difficult to employ, and the use of a damascene method is considered to be more promising. Many techniques in the damascene methods have been proposed. For example, Japanese laid-open patent application HEI 11-135506 describes a method for manufacturing a bonding pad section in a wiring structure that is formed by a damascene method.
According to the manufacturing method of Japanese laid-open patent application HEI 11-135506, the bonding pad section is formed in a manner described as follows. A copper wiring is formed over an uppermost dielectric layer by a damascene method. Then, a dielectric protection layer is formed over the entire surface of the dielectric layer and the copper wiring. The dielectric protection layer is patterned to form an opening region in a region where a bonding pad section is to be formed. Then, a copper oxide film on the surface of the copper wiring, which is formed during a step of removing a resist layer or a photo-etching step, is removed by a dry etching method. Thereafter, an aluminum layer is deposited thereon, and then a selective etching is conducted to pattern the aluminum layer such that the aluminum layer covers the opening region. In this manner, the bonding pad section in which the aluminum layer is deposited is formed over the copper wiring. The reference also describes a method of depositing an aluminum layer and then removing excess portions of the aluminum layer by a CMP method to embed the aluminum layer in the opening region, instead of selectively etching and patterning the aluminum layer after the aluminum layer is deposited.
The presence of the aluminum layer over the surface of the bonding pad section provides an improved bonding property with respect to gold and the like.
However, the process described above has the following problems. When the aluminum layer is patterned by a selective etching after the copper layer is formed, the step of forming the aluminum layer, the photolithography step and the etching step are required in addition to the damascene process. This increases the number of process steps. Furthermore, the selective etching requires an etcher for aluminum layers that are not used in the damascene process. When the aluminum layer is planarized by a CMP method after the copper wiring is formed, such a CMP step is added. As a result, the number of process steps increases. Also, the process described in the reference requires a step of removing copper oxide formed on the exposed surface of the copper wiring by a gas containing oxygen plasma and hydrofluoric acid.
Embodiments include a method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method. The method includes the steps of: (a) forming an opening region for the bonding pad section in an uppermost dielectric layer, the opening region being divided by dielectric layers of a specified pattern and including a plurality of partial opening sections; (b) successively forming a plurality of conduction layers comprising different materials over the dielectric layer; and (c) removing excess portions of the plurality of conduction layers and the dielectric layer to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers comprising different materials are exposed in each of the partial opening sections of the opening region.
Another embodiment relates to a semiconductor device including a plurality of wiring layers and dielectric layers interposed between the mutual wiring layers. A bonding pad section is located in an uppermost dielectric layer. The bonding pad section includes an opening region having a plurality of partial opening sections divided by dielectric layers. A plurality of conduction layers each comprising different materials and exposed are located in each of the partial opening sections.
Another embodiment relates to a method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method. The method includes forming an opening region for the bonding pad section in an uppermost dielectric layer, the opening region comprising a plurality of sub-openings divided from one another by dielectric walls. A plurality of conduction layers are formed into the sub-openings. Excess portions of the plurality of conduction layers and the dielectric layer are removed to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers are exposed in each of the sub-openings of the opening region.